The present invention relates to a semiconductor device and a manufacturing method thereof.
Techniques have been proposed for forming uneven surfaces such as trenches in the channel region of a substrate, to increase the effective channel width of a transistor without increasing in size.
For example, Japanese Patent Laid-Open No. H11-103058 and Japanese Patent Laid-Open No. S51-147269 describe a semiconductor device including a trench gate structure in which trenches are formed on the substrate surface. Japanese Patent Laid-Open No. 2007-5568 describes a semiconductor device in which a plurality of projecting silicon regions are formed in the width direction of a channel region formed between a source region and a drain region which are formed on a semiconductor substrate. A gate insulating film and a gate electrode are formed facing the channel region on the silicon projections. A reduction in the pitch of the gates reduces the width of the projections and achieves full depletion of a depletion layer in the projections during the operation of transistors, thus mitigating the short channel effect and improving the subthreshold slope (Japanese Patent Laid-Open No. 2005-085960). It is also possible to use such a decrease in the substrate bias dependence of threshold voltage due to such full depletion to advantage in an appropriate circuit configuration.
Japanese Patent Laid-Open 2009-54999 describes a semiconductor device formed on a semiconductor substrate of a first conductivity type and equipped with a trench structure having a depth intermittently changing in the gate width direction, a gate electrode formed, via a gate insulating film, inside a trench portion defined by the trench structure and on the upper surface of a planar portion, a source region of a second conductivity type formed on one side of the gate electrode, and a drain region of a second conductivity type formed on the other side of the gate electrode. Portions of the source region and the drain region which face each other with the trench portion there between have a depth equal to or greater than the depth of the trench structure from the upper surface to the bottom portion. Due to this structure, a current which otherwise flows mainly around the upper surfaces of the recessed portion of the gate electrode starts flowing more uniformly through the whole trench portion, resulting in an increase in the effective gate depth of the recessed portion whose depth changes in the gate width direction. According to this document, a semiconductor device having such a configuration can have reduced on-resistance and enhanced transistor power.
Japanese Patent Laid-Open No. 2008-192985 describes a semiconductor device in which trench portions are formed in the gate width direction so as to provide a well with unevenness and a gate electrode is formed inside and on the upper surface of the trench portion via an insulating film. A source region is formed on one side of the gate electrode in the gate length direction and a drain region is formed on the other side. The source region and the drain region both have a depth reaching the vicinity of the bottom portion of the gate electrode (the vicinity of the bottom portion of the trench portion). By forming the source region and the drain region of such a depth, a current which otherwise flows mainly around a shallow portion of the gate electrode starts flowing more uniformly through the whole trench portion and an effective gate width increases due to the unevenness formed in the well. According to this document, a semiconductor device having such a configuration can have reduced on-resistance and enhanced transistor power.
The present inventors have however found that these techniques have various problems. In the configuration described in Japanese Patent Laid-Open No. 2009-54999, a high-concentration n-type source region and drain region are in direct contact with a p well of a different conductivity type. Such a configuration makes it difficult to ensure a high breakdown voltage. For example, in order to ensure a breakdown voltage as high as about 20V or greater, it is preferred to provide, between the high-concentration source region and a channel region and between the high-concentration drain region and the channel region, a so-called offset region or a DDD (deeply doped drain) region, that is, a low-concentration region having a dopant concentration lower than that of the source region or the drain region.
When a low-concentration region is provided, on the other hand, the low-concentration region having a depth greater than that of a device isolation insulating film is likely to cause conduction through a substrate region below the device isolation insulating film, causing deterioration in device isolation ability.
According to the conventional techniques, it is impossible to ensure a high breakdown voltage as described above and at the same time, prevent deterioration of device isolation ability.